Software Engineering Manager, AI Kernels & Performance Optimization — MTIA Software

Meta designs and deploys its own AI systems. MTIA — the Meta Training and Inference Accelerator — is Meta's family of in-house AI accelerator ASICs, running recommendation and ranking workloads in production across Meta's data centers today and expanding into generative AI inference and training as successive silicon generations land.

The MTIA Software team is part of the AI & Compute Foundation (ACF) organization within Meta Infrastructure. We build the entire stack a chip vendor would normally supply — compiler and LLVM toolchain, runtime, kernel authoring frameworks and libraries, developer tooling, and deep PyTorch integration — co-designing it with the silicon teams generation over generation.

Within that stack, the AI Kernels and Performance Optimization team (KORE) owns the layer where silicon architecture meets arithmetic. Our mission is roofline-level performance and programmability at scale: we design and implement high-performance compute and communication kernels (GEMM, attention variants, normalization, collectives, elementwise and reduction fusions, sparse and quantized paths) against novel architectural features including matrix engines, on-chip reduction fabrics, and software-managed memory hierarchies. We ship kernel libraries with broad PyTorch operator coverage, build C++ and Python kernel authoring frameworks and DSL surfaces, and write production kernels against new architectures long before first silicon — turning hardware proposals into measured roofline evidence while the design can still change.

We are seeking a Software Engineering Manager to lead a team of kernel and performance engineers doing this work. You will own the performance of workloads that serve billions of people, drive technical strategy for kernel development and optimization, and build a team that can deliver roofline-level performance on MTIA accelerators. Your team will profile and root-cause performance across the full stack — instruction scheduling, memory hierarchy and DMA behavior, on-chip interconnect, multi-device collectives — and drive fixes to the right layer, whether that is the kernel, compiler, runtime, or hardware. You will partner closely with silicon architecture teams on hardware/software co-design, quantifying the value of proposed features with real kernels and advocating for the changes the software stack needs. This is a hands-on technical leadership role where you will contribute directly to architectural decisions while enabling your team to move with speed and clarity.