Technical Internship - Digital Design Verification [Japan]

This internship is located in Minato, Tokyo-to, Japan, starting from November 1, 2025, and concluding by September 30, 2026.

Responsibilities:

• Engage in new concepts and methodologies in the design verification community.
• Evaluate CAD tools and adopt them for production use.
• Help debug design verification issues and resolve them.
• Create scripts to enhance existing systems for design verification work.

Minimum Qualifications:

• Pursuing a BS, MS, or Ph.D. in Electrical Engineering, Computer Science, or Applied Physics.
• Holding a relevant work permit in Japan for the duration of the internship.
• Interest in Mixed-Signal LSI design, digital design, or verification.
• Experience with Verilog or System Verilog.

Preferred Qualifications:

• Verbal and written communication skills in English.
• Programming skills in languages such as Python, C/C++, or TCL.