STA Engineer (M, F, D)

This role is based in Munich, Germany.

Responsibilities:

Develop automated block and full chip level signoff flows, enable hierarchical timing flows, perform power optimizations, and drive custom IP integration.

Minimum Qualifications:

• MSEE or equivalent experience in Static Timing analysis
• Extensive experience with commercial STA tools
• Fluency in English

Preferred Qualifications:

• Familiarity with hierarchical design and timing convergence
• Experience with backend STA closure and signoff
• Good communication skills and team player