PMU Design Verification Intern (m/f/d)

This role is based in Nabern, Germany.

Responsibilities:

• Develop verification plans in coordination with design leads and architects.
• Build and maintain verification test bench components and environments.
• Generate directed and constrained random tests.
• Run simulations and debug design and environment issues.
• Craft automated verification flows for block and chip level verification.
• Apply knowledge of hardware description languages (VHDL/Verilog) and hardware verification languages (SystemVerilog/UVM).

Minimum Qualifications:

• Pursuing a BS or MS in Electrical Engineering or related field.
• Fluency in English and collaboration skills.
• Knowledge of SystemVerilog and UVM.
• Experience with Python, Perl or TCL.

Preferred Qualifications:

• Experience developing scalable and portable test-benches.
• Good understanding of digital design and mixed signal verification.