Formal Verification Framework for Hardware IPs Validation

This role is based in London, England, United Kingdom.

Responsibilities:

• Define comprehensive property sets for functional coverage of hardware models.
• Formalize verification properties using SVA.
• Execute formal proofs and analyze convergence behavior (accuracy VS execution time).
• Document methodology and best practices for the verification flow.

Minimum Qualifications:

• Currently enrolled in a Master's degree in Computer Science or equivalent.
• Knowledge of formal verification techniques.
• Knowledge of Verilog and/or VHDL.
• Passionate about mathematics.
• Scripting language knowledge (perl/python).
• Good written and verbal communication skills.
• Experience in working with international teams.
• Available for 6 months or more.

Preferred Qualifications:

• Bachelor in Computer Science or equivalent.