Circuit Design Intern (m/f/d)

This internship is based in Munich, Bavaria-Bayern, Germany.

Responsibilities:

• Work on new cell architectures and optimization for PPA improvement.
• Analyze layout and identify parasitic reducing options to improve cell PPA.
• Participate in technical discussions on new standard cell circuit development.
• Collaborate with different teams to ensure IP production and quality is met.

Minimum Qualifications:

• Currently enrolled in your penultimate year of studies in a CE, EE, CS or related field.
• Must be enrolled as a student for the full duration of the internship.
• Fluent English language skills (written and verbal).

Preferred Qualifications:

• Preliminary understanding of CMOS circuits and PPA oriented design.
• Understanding of layout design and parasitic optimization.
• Proficiency in scripting languages like Perl, Python, and Tcl.
• Excellent problem-solving and analytical thinking skills.
• Strong collaboration skills.