Cellular SoC Design and Frontend-STA Intern (M/F/D)

This internship is based in Germany.

Responsibilities:

Be a key part of the Cellular SoC Integration team, working with RTL designers and Physical designers on advanced technology nodes for constraint development and design-timing analysis.

Minimum Qualifications:

• Currently enrolled in a Master’s degree program in Electrical Engineering or equivalent.
• Solid understanding of Verilog and ability to analyze RTL/Netlist designs.
• Knowledge of scripting and programming with TCL, Python, Perl, or Make.
• Familiarity with ASIC/FPGA design processes, synthesis, and static timing analysis (STA).
• Excellent communication skills and ability to work in a multicultural environment.
• Proficiency in English.

Preferred Qualifications:

• Interest in leveraging AI/ML techniques to enhance workflows.
• Proficiency in Linux, revision control systems, and database management.