DFT Intern - Summer 2026

This internship is based in Santa Clara, CA.

Compensation:

$20 - $71/hour

Responsibilities:

• Design and implement test methodologies for large, complex, high-volume Digital ICs.
• Collaborate with logic designers to review and analyze IC designs and apply test techniques.
• Develop software to automate test logic insertion, timing analysis, vector generation, and validation.

Requirements:

• Pursuing a MS or PhD in Computer Architecture or Electrical Engineering.
• In-depth knowledge of automated testing techniques for semiconductors, including JTAG, BIST, and ATPG.
• Good programming skills in C++ and Perl5.