ASIC Engineer Intern, Design

This role is based in Bangalore, India.

Internship Duration:

12 to 16 weeks

Responsibilities:

• Participate in micro-architecture, design, and verification reviews.
• Design and develop RTL or HLS code for IPs.
• Analyze designs to enhance power, performance, and area (PPA).
• Support and develop verification infrastructure.
• Assist with simulation accelerators and post-silicon validation.

Minimum Qualifications:

• Currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, or related fields.
• Knowledge of Verilog or System Verilog or HLS.
• Understanding of computer architecture and logic design fundamentals.
• Must obtain work authorization in the country of employment at the time of hire.
• Intent to return to degree program after the internship.

Preferred Qualifications:

• Pursuing a Master's or PhD degree in relevant fields.
• Experience with Lint, synthesis, formal or physical design tools.
• Scripting experience with Python or Perl.
• Experience with high-performance computing and digital signal processing techniques.